On 04/08/2024 23:53, David Virag wrote:
> Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in
> theory supports USB3 SuperSpeed, but is only used as USB2 in all known
> devices.
>
> These clocks are needed for everything related to USB.
>
> While at it, also remove the CLK_SET_RATE_PARENT capability of
> CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed.
>
> Signed-off-by: David Virag <virag.david003@xxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynos7885.c | 73 ++++++++++++++++++++++------
> 1 file changed, 59 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
> index a0c9b7cc6942..637257a6f10e 100644
> --- a/drivers/clk/samsung/clk-exynos7885.c
> +++ b/drivers/clk/samsung/clk-exynos7885.c
> @@ -20,7 +20,7 @@
> #define CLKS_NR_TOP (CLK_MOUT_SHARED1_PLL + 1)
> #define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
> #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
> -#define CLKS_NR_FSYS (CLK_MOUT_FSYS_USB30DRD_USER + 1)
> +#define CLKS_NR_FSYS (CLK_FSYS_USB30DRD_REF_CLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -686,38 +686,66 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
> /* ---- CMU_FSYS ------------------------------------------------------------ */
>
> /* Register Offset definitions for CMU_FSYS (0x13400000) */
> -#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
> -#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
> -#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
> -#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
> -#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
> -#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
> -#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
> -#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
> -#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
> -#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
> -#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
> +#define PLL_LOCKTIME_PLL_USB 0x0000
> +#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
> +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
> +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
> +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
> +#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
> +#define PLL_CON0_PLL_USB 0x01a0
> +#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE 0x200c
> +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
> +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
> +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
> +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
> +#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
> +#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
> +#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL 0x2068
> +#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0 0x206c
> +#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1 0x2070
> +#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY 0x2074
> +#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK 0x2078
>
> static const unsigned long fsys_clk_regs[] __initconst = {
> + PLL_LOCKTIME_PLL_USB,
> PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
> PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
> PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
> PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
> PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
> + PLL_CON0_PLL_USB,
> + CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,
> CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
> CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
> CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
> CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
> CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
> CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
> + CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,
> + CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,
> + CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,
> + CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,
> + CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,
> };
>
> +static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
> + PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
> +};
> +
> +static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
> + PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
> + PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
> + pll_usb_rate_table),
> +};
> +
> +
Just one blank line.
> /* List of parent clocks for Muxes in CMU_FSYS */
> PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" };
> PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
> PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
> PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
> PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
> +PNAME(mout_usb_pll_p) = { "oscclk", "fout_usb_pll" };
>
> static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
> MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
> @@ -731,12 +759,16 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
> MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
> mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
> 4, 1, CLK_SET_RATE_PARENT, 0),
> - MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
> + MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
> mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
> - 4, 1, CLK_SET_RATE_PARENT, 0),
> + 4, 1),
> + nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,
> + PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
> };
>
> static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
> + GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",
> + CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
> CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
> GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
> @@ -752,9 +784,22 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
> GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
> "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
> 21, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",
> + "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
> + GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",
> + "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
> + GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",
> + "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
> + GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",
> + "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
> + GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",
> + CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
> +
Drop blank line
Best regards,
Krzysztof
