On Thu, Feb 08, 2024 at 01:50:34PM +0000, Tudor Ambarus wrote: > There are instances of the same IP that are configured by the integrator > with different FIFO depths. Introduce the fifo-depth property to allow > such nodes to specify their FIFO depth. > > We haven't seen SPI IPs with different FIFO depths for RX and TX, thus > introduce a single property. Some citation attached to this would be nice. "We haven't seen" offers no detail as to what IPs that allow this sort of configuration of FIFO size that you have actually checked. I went and checked our IP that we use in FPGA fabric, which has a configurable fifo depth. It only has a single knob for both RX and TX FIFOs. The Xilinx xps spi core also has configurable FIFOs, but again RX and TX sizes are tied there. At least that's a sample size of three. One of our guys is working on support for the IP I just mentioned and would be defining a vendor property for this, so Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks, Conor. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/spi/spi-controller.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml > index 524f6fe8c27b..99272e6f115e 100644 > --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml > @@ -69,6 +69,11 @@ properties: > Should be generally avoided and be replaced by > spi-cs-high + ACTIVE_HIGH. > > + fifo-depth: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Size of the data FIFO in bytes. > + > num-cs: > $ref: /schemas/types.yaml#/definitions/uint32 > description: > -- > 2.43.0.687.g38aa6559b0-goog >
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