On 19/12/2023 12:58, Varada Pavani wrote:
> Remove extra spaces and fix spelling mistakes in 'drivers/
> clk/samsung/clk-cpu.c' and 'drivers/clk/samsung/clk-cpu.h'
>
> Signed-off-by: Varada Pavani <v.pavani@xxxxxxxxxxx>
> ---
> drivers/clk/samsung/clk-cpu.c | 6 +++---
> drivers/clk/samsung/clk-cpu.h | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
> index 3e62ade120c5..18568b8b1b9b 100644
> --- a/drivers/clk/samsung/clk-cpu.c
> +++ b/drivers/clk/samsung/clk-cpu.c
> @@ -19,7 +19,7 @@
> * clock and the corresponding rate changes of the auxillary clocks of the CPU
> * domain. The platform clock driver provides a clock register configuration
> * for each configurable rate which is then used to program the clock hardware
> - * registers to acheive a fast co-oridinated rate change for all the CPU domain
> + * registers to achieve a fast co-oridinated rate change for all the CPU domain
> * clocks.
> *
> * On a rate change request for the CPU clock, the rate change is propagated
> @@ -181,7 +181,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
> * If the old parent clock speed is less than the clock speed of
> * the alternate parent, then it should be ensured that at no point
> * the armclk speed is more than the old_prate until the dividers are
> - * set. Also workaround the issue of the dividers being set to lower
> + * set. Also workaround the issue of the dividers being set to lower
Why? The double-space is correct.
> * values before the parent clock speed is set to new lower speed
> * (this can result in too high speed of armclk output clocks).
> */
> @@ -303,7 +303,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
> * If the old parent clock speed is less than the clock speed of
> * the alternate parent, then it should be ensured that at no point
> * the armclk speed is more than the old_prate until the dividers are
> - * set. Also workaround the issue of the dividers being set to lower
> + * set. Also workaround the issue of the dividers being set to lower
Why?
> * values before the parent clock speed is set to new lower speed
> * (this can result in too high speed of armclk output clocks).
> */
> diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
> index fc9f67a3b22e..e0a1651174e6 100644
> --- a/drivers/clk/samsung/clk-cpu.h
> +++ b/drivers/clk/samsung/clk-cpu.h
> @@ -33,7 +33,7 @@ struct exynos_cpuclk_cfg_data {
> * @hw: handle between CCF and CPU clock.
> * @alt_parent: alternate parent clock to use when switching the speed
> * of the primary parent clock.
> - * @ctrl_base: base address of the clock controller.
> + * @ctrl_base: base address of the clock controller.
Why only here and not in other places?
Best regards,
Krzysztof
