On 02/12/2023 02:36, Alim Akhtar wrote: > > >> -----Original Message----- >> From: Sam Protsenko <semen.protsenko@xxxxxxxxxx> >> Sent: Saturday, December 2, 2023 6:10 AM >> To: Peter Griffin <peter.griffin@xxxxxxxxxx> >> Cc: robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; >> mturquette@xxxxxxxxxxxx; conor+dt@xxxxxxxxxx; sboyd@xxxxxxxxxx; >> tomasz.figa@xxxxxxxxx; s.nawrocki@xxxxxxxxxxx; linus.walleij@xxxxxxxxxx; >> wim@xxxxxxxxxxxxxxxxxx; linux@xxxxxxxxxxxx; catalin.marinas@xxxxxxx; >> will@xxxxxxxxxx; arnd@xxxxxxxx; olof@xxxxxxxxx; >> gregkh@xxxxxxxxxxxxxxxxxxx; jirislaby@xxxxxxxxxx; >> cw00.choi@xxxxxxxxxxx; alim.akhtar@xxxxxxxxxxx; >> tudor.ambarus@xxxxxxxxxx; andre.draszik@xxxxxxxxxx; >> saravanak@xxxxxxxxxx; willmcvicker@xxxxxxxxxx; soc@xxxxxxxxxx; >> devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- >> samsung-soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; linux- >> gpio@xxxxxxxxxxxxxxx; linux-watchdog@xxxxxxxxxxxxxxx; kernel- >> team@xxxxxxxxxxx; linux-serial@xxxxxxxxxxxxxxx >> Subject: Re: [PATCH v5 14/20] pinctrl: samsung: Add gs101 SoC pinctrl >> configuration >> >> On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@xxxxxxxxxx> >> wrote: >>> >>> Add support for the pin-controller found on the gs101 SoC used in >>> Pixel 6 phones. >>> >>> Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx> >>> --- >>> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 159 ++++++++++++++++++ >>> drivers/pinctrl/samsung/pinctrl-exynos.c | 2 + >>> drivers/pinctrl/samsung/pinctrl-exynos.h | 34 ++++ >>> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + >>> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + >>> 5 files changed, 198 insertions(+) >>> >>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> index cb965cf93705..e1a0668ecb16 100644 >>> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> @@ -796,3 +796,162 @@ const struct samsung_pinctrl_of_match_data >> fsd_of_data __initconst = { >>> .ctrl = fsd_pin_ctrl, >>> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), >>> }; >>> + >>> +/* >>> + * bank type for non-alive type >>> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit >>> +field: 4) >>> + * (CONPDN bit field: 2, PUDPDN bit field: 4) */ static struct >>> +samsung_pin_bank_type gs101_bank_type_off = { >>> + .fld_width = { 4, 1, 4, 4, 2, 4, }, >>> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, }; >> >> This is just the same as exynos850_bank_type_off (100% duplication). >> Here is what I suggest. Now that it's obvious there is some common platform >> for moder Exynos SoCs, and it's probably Exynos9, I'd suggest next course of >> action (if maintainers agree): >> 1. Remove this one >> 2. Rename exynos850_bank_type_off to exynos9_bank_type_off >> 3. Use it for both gs101 and exynos850 >> >> Does it make sense? >> > My opinion is to reuse exynos850 for gs101 (wherever applicable), same philosophy was historically followed in this file. > That way (using exynos850 for gs101) things will be simple. > Adding exynos9_* is not adding any benefit, rather it create confusion. I don't see much value in renaming exynos850 bank type to exynos9 considering: 1. We don't really know the bank types for all of Exynos9xxx SoCs, 2. Exynos7885 also uses Exynos850 bank types. Exynos7885 was much earlier than Exynos9xxx family. Best regards, Krzysztof