On 09/11/2022 12:17, Sam Protsenko wrote:
> Hi Vivek,
>
> On Wed, 9 Nov 2022 at 11:54, Vivek Yadav <vivek.2311@xxxxxxxxxxx> wrote:
>>
>> From: Sriranjani P <sriranjani.p@xxxxxxxxxxx>
>>
>> Add SYSREG controller device node, which is available in PERIC and FSYS0
>> block of FSD SoC.
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
>> Signed-off-by: Pankaj Kumar Dubey <pankaj.dubey@xxxxxxxxxxx>
>> Cc: devicetree@xxxxxxxxxxxxxxx
>> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>
>> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
>> Signed-off-by: Sriranjani P <sriranjani.p@xxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/tesla/fsd.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
>> index f35bc5a288c2..3d8ebbfc27f4 100644
>> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
>> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
>> @@ -518,6 +518,16 @@
>> "dout_cmu_fsys1_shared0div4";
>> };
>>
>> + sysreg_peric: system-controller@14030000 {
>> + compatible = "tesla,sysreg_peric", "syscon";
>> + reg = <0x0 0x14030000 0x0 0x1000>;
>
> Probably not related to this particular patch, but does the "reg"
> really have to have those extra 0x0s? Why it can't be just:
>
> reg = <0x14030000 0x1000>;
>
> That comment applies to the whole dts/dtsi. Looks like #address-cells
> or #size-cells are bigger than they should be, or I missing something?
Yes, it looks like intention was to support some 64-bit addresses (maybe
as convention for arm64?) but none of upstreamed are above 32 bit range.
I don't have the manual/datasheet to judge whether any other
(non-upstreamed) nodes need 64bit addresses.
Best regards,
Krzysztof
