On 05/12/2021 16:32, David Virag wrote: > Provide dt-schema documentation for Exynos7885 SoC clock controller. > Description is modified from Exynos850 clock controller documentation as > I couldn't describe it any better, that was written by Sam Protsenko. > > Signed-off-by: David Virag <virag.david003@xxxxxxxxx> > --- > .../clock/samsung,exynos7885-clock.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml > > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml > new file mode 100644 > index 000000000000..9ec7358889d6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml > @@ -0,0 +1,166 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung Exynos7885 SoC clock controller > + > +maintainers: > + - Dávid Virág <virag.david003@xxxxxxxxx> > + - Chanwoo Choi <cw00.choi@xxxxxxxxxxx> > + - Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> > + - Sylwester Nawrocki <s.nawrocki@xxxxxxxxxxx> > + - Tomasz Figa <tomasz.figa@xxxxxxxxx> > + > +description: | > + Exynos7885 clock controller is comprised of several CMU units, generating > + clocks for different domains. Those CMU units are modeled as separate device > + tree nodes, and might depend on each other. The root clock in that root tree > + is an external clock:: OSCCLK (26 MHz). This external clock must be defined Double ':'. I think you meant only one > + as a fixed-rate clock in dts. > + Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> Best regards, Krzysztof
