On Sun, Nov 07, 2021 at 10:29:36PM +0200, Sam Protsenko wrote:
> On new Exynos chips (e.g. Exynos850 and Exynos9) the
> AUTOMATIC_WDT_RESET_DISABLE register was removed, and its value can be
> thought of as "always 0x0". Add correspondig quirk bit, so that the
> driver can omit accessing it if it's not present.
>
> This commit doesn't bring any functional change to existing devices, but
> merely provides an infrastructure for upcoming chips support.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
Reviewed-by: Guenter Roeck <linux@xxxxxxxxxxxx>
> ---
> Changes in v3:
> - Aligned arguments with opening parentheses
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v2:
> - Used quirks instead of callbacks for all added PMU registers
> - Used BIT() macro
> - Extracted splitting the s3c2410wdt_mask_and_disable_reset() function
> to separate patch
> - Extracted cleanup code to separate patch to minimize changes and
> ease the review and porting
>
> drivers/watchdog/s3c2410_wdt.c | 22 +++++++++++++---------
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0845c05034a1..2cc4923a98a5 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -59,10 +59,12 @@
> #define QUIRK_HAS_PMU_CONFIG (1 << 0)
> #define QUIRK_HAS_RST_STAT (1 << 1)
> #define QUIRK_HAS_WTCLRINT_REG (1 << 2)
> +#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
>
> /* These quirks require that we have a PMU register map */
> #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
> - QUIRK_HAS_RST_STAT)
> + QUIRK_HAS_RST_STAT | \
> + QUIRK_HAS_PMU_AUTO_DISABLE)
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> static int tmr_margin;
> @@ -137,7 +139,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
> .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> .rst_stat_bit = 20,
> .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
> - | QUIRK_HAS_WTCLRINT_REG,
> + | QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_AUTO_DISABLE,
> };
>
> static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> @@ -147,7 +149,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> .rst_stat_bit = 9,
> .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
> - | QUIRK_HAS_WTCLRINT_REG,
> + | QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_AUTO_DISABLE,
> };
>
> static const struct s3c2410_wdt_variant drv_data_exynos7 = {
> @@ -157,7 +159,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = {
> .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> .rst_stat_bit = 23, /* A57 WDTRESET */
> .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
> - | QUIRK_HAS_WTCLRINT_REG,
> + | QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_AUTO_DISABLE,
> };
>
> static const struct of_device_id s3c2410_wdt_match[] = {
> @@ -213,11 +215,13 @@ static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
> if (mask)
> val = mask_val;
>
> - ret = regmap_update_bits(wdt->pmureg,
> - wdt->drv_data->disable_reg,
> - mask_val, val);
> - if (ret < 0)
> - goto error;
> + if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
> + ret = regmap_update_bits(wdt->pmureg,
> + wdt->drv_data->disable_reg, mask_val,
> + val);
> + if (ret < 0)
> + goto error;
> + }
>
> ret = regmap_update_bits(wdt->pmureg,
> wdt->drv_data->mask_reset_reg,
> --
> 2.30.2
>
