> >>> #define PCLK_AVAIL_MIN 70000000 > >>> -#define PCLK_AVAIL_MAX 133000000 > >>> +#define PCLK_AVAIL_MAX 167000000 > >>> > >> > >> I'm not sure but doesn't the maximum clock frequency depend on a > >> given machine? Is it true for all machines using different SoC? > > > > Regarding pclk(sclk_unipro)of the ufs, it can be defined by > mux(MUX_CLK_FSYS2_UFS_EMBD). > > It can be either 167MHz or 160MHz. And it can be defined by OSCCLK(26MHz) > as well. The value was up to 133Mhz in case of exynos7 but can be extended > up to 167MHz for later SoCs, AFAIK. > > Oscillator clock frequency could be different according to machine. And > what if UFS driver is enabled for other machine using Exynos7? Is it true > to use a fixed 167MHz frequency for these machines? > I think you could get a proper pclk frequency from device tree specific to > machine. The actual pclk value will be get by CCF's clk_get_rate. PCLK_AVAIL_MAX represents the available maximum value of UFS's pclk to find an optimal value of unipro clock. I just extend the maximum pclk rate from 133MHz to 167MHz. The divider will be calculated according to the actual pclk value :) [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/ufs/ufs-exynos.c?h=v5.15-rc3#n287 Best Regards, Chanho Park
