Hi Chanho,
21. 9. 17. 오후 3:54에 Chanho Park 이(가) 쓴 글:
> To support 167MHz PCLK, we need to adjust the maximum value.
>
> Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
> ---
> drivers/scsi/ufs/ufs-exynos.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
> index dadf4fd10dd8..0a31f77a5f48 100644
> --- a/drivers/scsi/ufs/ufs-exynos.h
> +++ b/drivers/scsi/ufs/ufs-exynos.h
> @@ -99,7 +99,7 @@ struct exynos_ufs;
> #define PA_HIBERN8TIME_VAL 0x20
>
> #define PCLK_AVAIL_MIN 70000000
> -#define PCLK_AVAIL_MAX 133000000
> +#define PCLK_AVAIL_MAX 167000000
>
I'm not sure but doesn't the maximum clock frequency depend on a given machine? Is it true for all machines using different SoC?
Thanks,
Inki Dae
> struct exynos_ufs_uic_attr {
> /* TX Attributes */
>
