RE: [PATCH v3 11/17] scsi: ufs: ufs-exynos: add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option

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>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@xxxxxxxxxxx]
>Sent: Friday, September 17, 2021 12:25 PM
>To: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>; Avri Altman
><avri.altman@xxxxxxx>; James E . J . Bottomley <jejb@xxxxxxxxxxxxx>; Martin
>K . Petersen <martin.petersen@xxxxxxxxxx>; Krzysztof Kozlowski
><krzysztof.kozlowski@xxxxxxxxxxxxx>
>Cc: Bean Huo <beanhuo@xxxxxxxxxx>; Bart Van Assche
><bvanassche@xxxxxxx>; Adrian Hunter <adrian.hunter@xxxxxxxxx>; Christoph
>Hellwig <hch@xxxxxxxxxxxxx>; Can Guo <cang@xxxxxxxxxxxxxx>; Jaegeuk Kim
><jaegeuk@xxxxxxxxxx>; Gyunghoon Kwon <goodjob.kwon@xxxxxxxxxxx>;
>linux-samsung-soc@xxxxxxxxxxxxxxx; linux-scsi@xxxxxxxxxxxxxxx; Chanho Park
><chanho61.park@xxxxxxxxxxx>; Kiwoong Kim <kwmad.kim@xxxxxxxxxxx>
>Subject: [PATCH v3 11/17] scsi: ufs: ufs-exynos: add
>EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option
>
>To skip exynos_ufs_config_phy_*_attr settings for exynos-ufs variant, this patch
>provides EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR as an opts flag.
>
Please add a bit more information on why this has to be skipped for this HCI.

Thanks

>Cc: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
>Cc: Kiwoong Kim <kwmad.kim@xxxxxxxxxxx>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
>Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
>---
> drivers/scsi/ufs/ufs-exynos.c | 6 ++++--  drivers/scsi/ufs/ufs-exynos.h | 1 +
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>a3160d9bd234..73833c186ca9 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -831,8 +831,10 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
>
> 	/* m-phy */
> 	exynos_ufs_phy_init(ufs);
>-	exynos_ufs_config_phy_time_attr(ufs);
>-	exynos_ufs_config_phy_cap_attr(ufs);
>+	if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
>+		exynos_ufs_config_phy_time_attr(ufs);
>+		exynos_ufs_config_phy_cap_attr(ufs);
>+	}
>
> 	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index
>bc4b8b0324bd..a0899aaa902e 100644
>--- a/drivers/scsi/ufs/ufs-exynos.h
>+++ b/drivers/scsi/ufs/ufs-exynos.h
>@@ -200,6 +200,7 @@ struct exynos_ufs {
> #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
> #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
> #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
>+#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR	BIT(5)
> };
>
> #define for_each_ufs_rx_lane(ufs, i) \
>--
>2.33.0






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