On 14/09/2021 17:56, Sam Protsenko wrote: > pll0831x PLL is used in Exynos850 SoC for top-level fractional PLLs. The > code was derived from very similar pll36xx type, with next differences: > > 1. Lock time for pll0831x is 500*P_DIV, when for pll36xx it's 3000*P_DIV > 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require > performing PLL lock procedure (which is done in pll36xx > implementation) > 3. The offset from PMS-values register to K-value register is 0x8 for > pll0831x, when for pll36xx it's 0x4 > > When defining pll0831x type, CON3 register offset should be provided as > a "con" parameter of PLL() macro, like this: > > PLL(pll_0831x, 0, "fout_mmc_pll", "oscclk", > PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, pll0831x_26mhz_tbl), > > To define PLL rates table, one can use PLL_36XX_RATE() macro, e.g.: > > PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124) > > as it's completely appropriate for pl0831x type and there is no sense in > duplicating that. > > If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be > possible to set new rate, with next error showing in kernel log: > > Could not lock PLL fout_mmc_pll > > That can happen for example if bootloader clears that bit beforehand. > PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was > cleared, it's assumed it was done for a reason and it shouldn't be > possible to change that PLL's rate at all. > > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> > --- > drivers/clk/samsung/clk-pll.c | 105 ++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 106 insertions(+) > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> Best regards, Krzysztof
