On 14/09/2021 17:56, Sam Protsenko wrote: > pll0822x PLL is used in Exynos850 SoC for top-level integer PLLs. The > code was derived from very similar pll35xx type, with next differences: > > 1. Lock time for pll0822x is 150*P_DIV, when for pll35xx it's 270*P_DIV > 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require > performing PLL lock procedure (which is done in pll35xx > implementation) > > When defining pll0822x type, CON3 register offset should be provided as > a "con" parameter of PLL() macro, like this: > > PLL(pll_0822x, 0, "fout_shared0_pll", "oscclk", > PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > exynos850_shared0_pll_rates), > > To define PLL rates table, one can use PLL_35XX_RATE() macro, e.g.: > > PLL_35XX_RATE(26 * MHZ, 1600 * MHZ, 800, 13, 0) > > as it's completely appropriate for pl0822x type and there is no sense in > duplicating that. > > If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be > possible to set new rate, with next error showing in kernel log: > > Could not lock PLL fout_shared1_pll > > That can happen for example if bootloader clears that bit beforehand. > PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was > cleared, it's assumed it was done for a reason and it shouldn't be > possible to change that PLL's rate at all. > > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> > --- > drivers/clk/samsung/clk-pll.c | 91 +++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 92 insertions(+) > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> Best regards, Krzysztof
