Hi Marek,
On 5/6/20 10:26 PM, Marek Szyprowski wrote:
> The TOP 'aclk*_isp', 'aclk550_cam', 'gscl_wa' and 'gscl_wb' clocks must
> be kept enabled all the time to allow proper access to power management
> control for the ISP and CAM power domains. The last two clocks, although
> related to GScaler device and GSCL power domain, provides also the
> I_WRAP_CLK signal to MIPI CSIS0/1 devices, which are a part of CAM power
> domain and are needed for proper power on/off sequence.
>
> Currently there are no drivers for the devices, which are part of CAM and
> ISP power domains yet. This patch only fixes the race between disabling
> the unused power domains and disabling unused clocks, which randomly
> resulted in the following error during boot:
>
> Power domain CAM disable failed
> Power domain ISP disable failed
>
> Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical")
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index c9e5a1fb6653..edb2363c735a 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -540,7 +540,7 @@ static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
>
> static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
> GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
> - GATE_BUS_TOP, 24, 0, 0),
> + GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
> GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
> GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
> };
> @@ -943,25 +943,25 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
> GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
> GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
> - GATE_BUS_TOP, 5, 0, 0),
> + GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
> GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
> GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
> GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
> GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
> GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
> - GATE_BUS_TOP, 8, 0, 0),
> + GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
> GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
> GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
> GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
> GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
> GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
> - GATE_BUS_TOP, 13, 0, 0),
> + GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
> GATE(0, "aclk166", "mout_user_aclk166",
> GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
> GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
> GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
> GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
> - GATE_BUS_TOP, 16, 0, 0),
> + GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
> GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
> GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
> GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
> @@ -1161,8 +1161,10 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> GATE_IP_GSCL1, 3, 0, 0),
> GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
> GATE_IP_GSCL1, 4, 0, 0),
> - GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
> - GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
> + GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
> + CLK_IS_CRITICAL, 0),
> + GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
> + CLK_IS_CRITICAL, 0),
> GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
> GATE_IP_GSCL1, 16, 0, 0),
> GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
>
Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
Thanks.
--
Best Regards,
Chanwoo Choi
Samsung Electronics
