On 12/13/19 08:11, Marek Szyprowski wrote: > The real issue here is that some SoC internal busses (not assigned to > any driver at all) are sourced from the same MUX, which that patch > flagged as CRITICAL without any additional gates, thus if the only > client of that MUX disables its gate clock, the whole path up to the > root PLL is disabled what causes the HW issue. The driver (or user via > dts) might change the root PLL, so that CRITICAL flag cannot be moved to > the top clock in this hierarchy. > > I can change that CRITICAL flag to a explicit call to > clk_prepare_enable() during exynos542x-clk driver probe, but IMHO the > flag better fits in such case. I would prefer an explicit clk_prepare_enable() call, similarly as it is done in drivers/clk/samsung/clk-exynos-audss.c. This would somewhat separate proper clocks definition from workarounds. The CLK_IS_CRITICAL flag might be a bit misleading IMO because the clock for which it is being added now doesn't have gating ability. The flag really applies to some root PLL clock which is behind few other muxes going up in the clk tree. -- Regards Sylwester
