Hi Claudiu,
On Fri, Aug 30, 2024 at 3:02 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> the tamper detector and a small general usage memory of 128B. Add
> documentation for it.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> ---
>
> Changes in v3:
> - moved the file to clock dt bindings directory as it is the
> only functionality supported at the moment; the other functionalities
> (tamper detector, SRAM) are offered though register spreaded
> though the address space of the VBATTB IP and not actually
> individual devices; the other functionalities are not
> planned to be supported soon and if they will be I think they
> fit better on auxiliary bus than MFD
> - dropped interrupt names as requested in the review process
> - dropped the inner node for clock controller
> - added #clock-cells
> - added rtx clock
> - updated description for renesas,vbattb-load-nanofarads
> - included dt-bindings/interrupt-controller/irq.h in examples section
Thanks for the update!
LGTM, modulo issues pointed out in other review comments.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
