Am Dienstag, 20. M?rz 2018, 03:06:29 CET schrieb Lin Huang: > These clocks do not assign default clock frequency, and use the > default cru register value to get frequency, so if cpll increase > frequency, these clocks also increase their frequency, that may > exceed their signed off frequency. So assign default clock for > them to avoid it. > > NOTE: on none of the boards currently in mainline do we expect > CPLL to be anything other than 800 MHz, but some future boards > might have it. It's still good to be explicit about the clock > rates to make diffing against future boards easier and also to > rely less on BIOS muxing. > > Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401 > Signed-off-by: Lin Huang <hl at rock-chips.com> > Reviewed-by: Douglas Anderson <dianders at chromium.org> applied for 4.17 (but will most likely move to 4.18) with some changes: - dropped Change-Id - fixed duplicate assigned clocks for dp node - grouped aclk_vio and aclk_hdcp into one line in cru nodes - moved assigned clocks Heiko
