Am Dienstag, 20. M?rz 2018, 03:06:28 CET schrieb Lin Huang: > Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, > and these two PLL may change their frequency. If we do not > assign right id to pclk_ddr and hclk_sd, they will alway use > default cur register value, and may get the frequency > exceed their signed off frequency. So assign correct Id > for them, then we can assign frequency for them in dts. > > Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee > Signed-off-by: Lin Huang <hl at rock-chips.com> > Reviewed-by: Douglas Anderson <dianders at chromium.org> > Reviewed-by: Shawn Lin <shawn.lin at rock-chips.com> applied for 4.17 after dropping the Change-Id Thanks Heiko
