[PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Am Dienstag, 20. M?rz 2018, 03:23:41 CET schrieb hl:
> On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> > On 2018/3/20 10:06, Lin Huang wrote:
> >> These clocks do not assign default clock frequency, and use the
> >> default cru register value to get frequency, so if cpll increase
> >> frequency, these clocks also increase their frequency, that may
> >> exceed their signed off frequency. So assign default clock for
> >> them to avoid it.
> >> 
> >> NOTE: on none of the boards currently in mainline do we expect
> >> CPLL to be anything other than 800 MHz, but some future boards
> >> might have it. It's still good to be explicit about the clock
> >> rates to make diffing against future boards easier and also to
> >> rely less on BIOS muxing.
> >> 
> >> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> > 
> > Should remove Change-Id for future patch(es), thought Heiko may help
> > do it when applied.
> 
> Opp, sorry for that.

Yep, I can drop the changeId when applying



[Index of Archives]     [LM Sensors]     [Linux Sound]     [ALSA Users]     [ALSA Devel]     [Linux Audio Users]     [Linux Media]     [Kernel]     [Gimp]     [Yosemite News]     [Linux Media]

  Powered by Linux