RE: [PATCH v6 11/12] irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}

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Hi Thomas,

Updated patch#11 by using field_width as macro parameter. 

Cheers,
Biju

> -----Original Message-----
> From: Biju Das
> Sent: 24 February 2025 16:41
> To: Thomas Gleixner <tglx@xxxxxxxxxxxxx>; Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>; biju.das.au
> <biju.das.au@xxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx
> Subject: RE: [PATCH v6 11/12] irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}
> 
> Hi Thomas,
> 
> > -----Original Message-----
> > From: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> > Sent: 24 February 2025 15:53
> > Subject: RE: [PATCH v6 11/12] irqchip/renesas-rzv2h: Update macros
> > ICU_TSSR_TSSEL_{MASK,PREP}
> >
> > On Mon, Feb 24 2025 at 13:59, Biju Das wrote:
> > >> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> > >> > -#define ICU_TSSR_TSSEL_PREP(tssel, n)          ((tssel) << ((n) * 8))
> > >> > -#define ICU_TSSR_TSSEL_MASK(n)                 ICU_TSSR_TSSEL_PREP(0x7F, n)
> > >> > +#define ICU_TSSR_TSSEL_PREP(tssel, n, f_width) ((tssel) << ((n) * (f_width)))
> > >> > +#define ICU_TSSR_TSSEL_MASK(n, _field_width)   \
> > >>
> > >> Nit: please use f_width or field_width consistently.
> > >
> > > With field_width there was some alignment issue, that is the reason
> > > it is shortened to f_width.
> > >
> > > If there are no other comments for this patch, I will switch using
> > > field_width in the next version.
> >
> > If this is the only change, then please just post an updated version
> > of _this_ patch (11/12) as a reply to the patch itself. No need to
> > resend the whole series for that cosmetic change,

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 8d0bd4d69de2..7bc4397ec149 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,13 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
-#define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
+#define ICU_TSSR_TSSEL_PREP(tssel, n, field_width)	((tssel) << ((n) * (field_width)))
+#define ICU_TSSR_TSSEL_MASK(n, field_width)	\
+({\
+		typeof(field_width) (_field_width) = (field_width); \
+		ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
+})
+
 #define ICU_TSSR_TIEN(n, field_width)	\
 ({\
 		typeof(field_width) (_field_width) = (field_width); \
@@ -326,8 +331,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	guard(raw_spinlock)(&priv->lock);
 
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
-	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
-	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
+	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien);
+	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width);
 
 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
-- 
2.43.0





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