Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 24 February 2025 13:52
> Subject: Re: [PATCH v6 11/12] irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}
>
> Hi Biju,
>
> On Mon, 24 Feb 2025 at 14:13, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H.
> > Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved
> > bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both
> > SoCs for extracting TSSEL and then update the macros
> > ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK for supporting both SoCs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v5->v6:
> > * Dropped Rb tag from Geert as it retain macros instead of dropping it.
> > * Retained the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK by
> > adding field_width parameter.
> > v4->v5:
> > * Used tssr_shift_factor in rzv2h_tint_set_type to optimize the
> > calculation.
> > * Dropped unnecessary parenthesis for calculating tssr.
> > * Added Rb tag from Geert.
>
> Thanks for the updates!
>
> > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > @@ -64,8 +64,13 @@
> > #define ICU_TINT_LEVEL_HIGH 2
> > #define ICU_TINT_LEVEL_LOW 3
> >
> > -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8))
> > -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n)
> > +#define ICU_TSSR_TSSEL_PREP(tssel, n, f_width) ((tssel) << ((n) * (f_width)))
> > +#define ICU_TSSR_TSSEL_MASK(n, _field_width) \
>
> Nit: please use f_width or field_width consistently.
With field_width there was some alignment issue, that is
the reason it is shortened to f_width.
If there are no other comments for this patch, I will switch using
field_width in the next version.
Cheers,
Biju
