Hi Shimoda-san,
On Thu, Jul 11, 2024 at 10:29 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > From: Geert Uytterhoeven, Sent: Wednesday, July 10, 2024 10:11 PM
> > Currently, almost all PLLs on R-Car Gen4 SoCs are modelled as fixed
> > divider clocks, based on the state of the mode pins. The only exception
> > is PLL2 on R-Car V4H, which uses a custom clock driver to support High
> > Performance mode on the Cortex-A76 CPU cores.
> >
> > However, the boot loader stack may have changed the actual PLL
> > configuration from the default, leading to incorrect clock frequencies.
> > A typical sympton is a CPU core running much slower than reported by
> > Linux.
> >
> > This patch series enhances PLL support on R-Car Gen4 support by
> > obtaining the actual PLL configuration from the hardware. As these PLLs
> > can be configured for fractional multiplication, an old patch to add
> > support fractional multiplication is revived, too. Of course some
> > cleanups are included, too.
>
> Thank you for the patches! I reviewed all patches and it seems good.
> # I sent a nit comment on the patch 4/14 though.
>
> So,
>
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Thank you!
> > Note that struct rcar_gen4_cpg_pll_config still contains the default
> > multipliers and dividers for PLL1/2/3/4/6, while they are no longer
> > used. Probably they should be removed, too. Or do you think we should
> > retain them for documentation purposes>
>
> I think that retaining them is good for the documentation purposes.
Another option is to remove the members, but keep the values
in the comments above the SoC-specific instances.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
