On Wed, Jul 10, 2024 at 3:10 PM Geert Uytterhoeven
<geert+renesas@xxxxxxxxx> wrote:
> R-Car Gen4 PLLs support fractional multiplication, which can improve
> accuracy when configuring a specific frequency.
>
> Add support for fractional multiplication to the custom clock driver
> for PLLs, which is currently used only for PLL2 on R-Car V4H.
> While at it, add the missing blank line after the function.
>
> Note that Fractional Multiplication is not enabled by the driver,
> but used only if the boot loaded enabled it before.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> --- a/drivers/clk/renesas/rcar-gen4-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen4-cpg.c
> @@ -77,17 +79,26 @@ static unsigned long cpg_pll_8_25_clk_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
> - unsigned int mult;
> -
> - mult = FIELD_GET(CPG_PLLxCR0_NI8, readl(pll_clk->pllcr0_reg)) + 1;
> + u32 cr0 = readl(pll_clk->pllcr0_reg);
> + unsigned int ni, nf;
> + unsigned long rate;
> +
> + ni = (FIELD_GET(CPG_PLLxCR0_NI8, cr0) + 1) * 2;
> + rate = parent_rate * ni;
> + if (cr0 & CPG_PLLxCR0_SSMODE_FM) {
> + nf = FIELD_GET(CPG_PLLxCR1_NF25, readl(pll_clk->pllcr1_reg));
> + rate += ((u64)parent_rate * nf) >> 24;
This (and every other similar calculation in this series) can use
mul_u64_u32_shr(), for better performance when reused on 32-bit,
at the cost of a slight code increase on arm64.
> + }
>
> - return parent_rate * mult * 2;
> + return rate;
> }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
