Hello Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, July 10, 2024 10:11 PM
>
> Hi all,
>
> Currently, almost all PLLs on R-Car Gen4 SoCs are modelled as fixed
> divider clocks, based on the state of the mode pins. The only exception
> is PLL2 on R-Car V4H, which uses a custom clock driver to support High
> Performance mode on the Cortex-A76 CPU cores.
>
> However, the boot loader stack may have changed the actual PLL
> configuration from the default, leading to incorrect clock frequencies.
> A typical sympton is a CPU core running much slower than reported by
> Linux.
>
> This patch series enhances PLL support on R-Car Gen4 support by
> obtaining the actual PLL configuration from the hardware. As these PLLs
> can be configured for fractional multiplication, an old patch to add
> support fractional multiplication is revived, too. Of course some
> cleanups are included, too.
Thank you for the patches! I reviewed all patches and it seems good.
# I sent a nit comment on the patch 4/14 though.
So,
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> Note that struct rcar_gen4_cpg_pll_config still contains the default
> multipliers and dividers for PLL1/2/3/4/6, while they are no longer
> used. Probably they should be removed, too. Or do you think we should
> retain them for documentation purposes>
I think that retaining them is good for the documentation purposes.
Best regards,
Yoshihiro Shimoda
> Thanks for your comments!
>
> Geert Uytterhoeven (14):
> clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions
> clk: renesas: rcar-gen4: Clarify custom PLL clock support
> clk: renesas: rcar-gen4: Use FIELD_GET()
> clk: renesas: rcar-gen4: Use defines for common CPG registers
> clk: renesas: rcar-gen4: Add support for fractional multiplication
> clk: renesas: rcar-gen4: Add support for variable fractional PLLs
> clk: renesas: rcar-gen4: Add support for fixed variable PLLs
> clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
> clk: renesas: r8a779a0: Use defines for PLL control registers
> clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
> clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
> clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
> clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
> clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
>
> drivers/clk/renesas/r8a779a0-cpg-mssr.c | 25 +--
> drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +-
> drivers/clk/renesas/r8a779g0-cpg-mssr.c | 26 +--
> drivers/clk/renesas/r8a779h0-cpg-mssr.c | 22 +--
> drivers/clk/renesas/rcar-gen4-cpg.c | 209 ++++++++++++++++--------
> drivers/clk/renesas/rcar-gen4-cpg.h | 28 +++-
> 6 files changed, 209 insertions(+), 119 deletions(-)
>
> --
> 2.34.1
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
