Hello Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, July 10, 2024 10:11 PM
>
> Add symbolic definitions for common CPG registers.
> Replace hardcoded register offsets by the new definitions.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> drivers/clk/renesas/r8a779a0-cpg-mssr.c | 12 ++++++------
> drivers/clk/renesas/r8a779f0-cpg-mssr.c | 6 +++---
> drivers/clk/renesas/r8a779g0-cpg-mssr.c | 12 ++++++------
> drivers/clk/renesas/r8a779h0-cpg-mssr.c | 12 ++++++------
> drivers/clk/renesas/rcar-gen4-cpg.h | 6 ++++++
> 5 files changed, 27 insertions(+), 21 deletions(-)
<snip>
> diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
> index d0329ac84730d681..748c69240dae755f 100644
> --- a/drivers/clk/renesas/rcar-gen4-cpg.h
> +++ b/drivers/clk/renesas/rcar-gen4-cpg.h
> @@ -67,6 +67,12 @@ struct rcar_gen4_cpg_pll_config {
> u8 osc_prediv;
> };
>
> +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
> +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
> +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
nit:
Perhaps, the definitions should be ordered by the registers' offsets like below:
+#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
Best regards,
Yoshihiro Shimoda
> +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
> +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
> +
> struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
> const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
> struct clk **clks, void __iomem *base,
> --
> 2.34.1
