From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM).
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v6->v7:
* No change
v5->v6:
* No change
v4->v5:
* No change
v3->v4:
* No change
v2->v3:
* Added Rb tag from Geert.
v1->v2:
* Added Rb tag from Krzysztof and the keep the Rb tag as the below
* changes
are trivial
* Updated the description for APB clock
* Added resets required property
* Updated the example with resets property
.../bindings/pwm/renesas,rzv2m-pwm.yaml | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
new file mode 100644
index 000000000000..ddeed7550923
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2{M, MA} PWM Timer (PWM)
+
+maintainers:
+ - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
+
+description: |
+ The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the
+ following functions
+ * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz).
+ * The frequency division ratio for internal counter operation is selectable
+ as PWM_CLK divided by 1, 16, 256, or 2048.
+ * The period as well as the duty cycle is adjustable.
+ * The low-level and high-level order of the PWM signals can be inverted.
+ * The duty cycle of the PWM signal is selectable in the range from 0 to 100%.
+ * The minimum resolution is 20.83 ns.
+ * Three interrupt sources: Rising and falling edges of the PWM signal and
+ clearing of the counter
+ * Counter operation and the bus interface are asynchronous and both can
+ operate independently of the magnitude relationship of the respective
+ clock periods.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a09g011-pwm # RZ/V2M
+ - renesas,r9a09g055-pwm # RZ/V2MA
+ - const: renesas,rzv2m-pwm
+
+ reg:
+ maxItems: 1
+
+ '#pwm-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB clock
+ - description: PWM clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: pwm
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+allOf:
+ - $ref: pwm.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a09g011-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pwm8: pwm@a4010400 {
+ compatible = "renesas,r9a09g011-pwm", "renesas,rzv2m-pwm";
+ reg = <0xa4010400 0x80>;
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM8_CLK>;
+ clock-names = "apb", "pwm";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ #pwm-cells = <2>;
+ };
--
2.34.1
