As per section "8.8.2 Clear Timing of Interrupt Cause" of the RZ/G2L
hardware manual (Rev.1.45 Jan, 2024), it is mentioned that we need to
clear the interrupt cause flag in the isr. It takes some time for the
cpu to clear the interrupt cause flag. Therefore, to prevent another
occurrence of interrupt due to this delay, the interrupt cause flag
is read after clearing.
Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver")
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
drivers/irqchip/irq-renesas-rzg2l.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 9494fc26259c..46f9b07e0e8a 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -111,8 +111,11 @@ static void rzg2l_tint_eoi(struct irq_data *d)
u32 reg;
reg = readl_relaxed(priv->base + TSCR);
- if (reg & bit)
+ if (reg & bit) {
writel_relaxed(reg & ~bit, priv->base + TSCR);
+ /* Read to avoid irq generation due to irq clearing delay */
+ readl_relaxed(priv->base + TSCR);
+ }
}
static void rzg2l_irqc_eoi(struct irq_data *d)
--
2.25.1
