Hi Claudiu,
On Mon, Dec 4, 2023 at 8:41 AM claudiu beznea <claudiu.beznea@xxxxxxxxx> wrote:
> On 01.12.2023 19:35, Geert Uytterhoeven wrote:
> > On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >>
> >> Add Ethernet nodes available on RZ/G3S (R9A08G045).
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >
> > Thanks for your patch!
> >
> >> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> >> @@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 {
> >> status = "disabled";
> >> };
> >>
> >> + eth0: ethernet@11c30000 {
> >> + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
> >> + reg = <0 0x11c30000 0 0x10000>;
> >> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> >> + interrupt-names = "mux", "fil", "arp_ns";
> >> + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
> >> + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
> >> + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
> >> + clock-names = "axi", "chi", "refclk";
> >> + resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
> >> + power-domains = <&cpg>;
> >
> > Perhaps add a default phy mode, like on other SoCs?
> >
> > phy-mode = "rgmii"';
>
> I skipped this (even it was available on the other SoCs) as I consider the
> phy-mode is board specific.
IC. Still, it's good to have some consistency across boards.
> > Also missing:
> >
> > #address-cells = <1>;
> > #size-cells = <0>;
>
> Same for these.
These are required, and always have the same values, so it makes more
sense to have them in the SoC .dtsi file, once.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
