From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Add Ethernet nodes available on RZ/G3S (R9A08G045).
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 6c7b29b69d0e..1caa0587fdd4 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -149,6 +149,38 @@ sdhi2: mmc@11c20000 {
status = "disabled";
};
+ eth0: ethernet@11c30000 {
+ compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
+ reg = <0 0x11c30000 0 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
+ <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
+ <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ eth1: ethernet@11c40000 {
+ compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
+ reg = <0 0x11c40000 0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
+ <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
+ <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@12400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.39.2
