Re: [PATCH net] net: ethernet: renesas: rswitch Fix PHY station management clock setting

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> Yes, the original version was tested on Spider board.
> The original version's MDC frequency was 25MHz.
> And the PHY (Marvell 88E2110) on Spider board can use such frequency,
> IIUC because the MDC period is 35 ns (so 28.57143MHz).

25MHz is way above anything i've tested.

> However, I don't know why this setting cannot work on the Starter Kit board
> because the board also has the same PHY. I guess that this is related to
> board design, especially voltage of I/O (Spider = 1.8V, Starter Kit = 3.3V).

I've had boards which will not work at 2.5Mhz until the pull up
resistor was changed to make the waveform compliant. So it probably is
related to the board.

> Anyway, changing the MDC frequency from 25MHz to 2.5MHz works correctly on
> both Spider and Starter Kit. So, I would like to apply the v3 patch [1] for safe.

O.K. That makes sense. If you want to support the higher speed, you
could implement the device tree property:


  clock-frequency:
    description:
      Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
      defined 2.5MHz should only be used when all devices on the bus support
      the given clock speed.

	Andrew



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