Hi Geert,
Thanks for your work.
On 2023-02-14 11:02:07 +0100, Geert Uytterhoeven wrote:
> According to the R-Car Series, 3rd Generation Hardware User’s Manual
> Rev. 2.30, the parent clock of the Video Input Module (VIN) on R-Car D3
> is S3D1. Update the driver to match the documentation.
>
> This has no functional impact, as both S1D2 and S3D1 have the same clock
> rate, and are always-on clocks.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> To be queued in renesas-clk-for-v6.4.
>
> drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> index 24ba9093a72f7341..3a73f6f911dd5160 100644
> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
> DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
> DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
> DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
> - DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
> + DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
> DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
> DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
> DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
> --
> 2.34.1
>
--
Kind Regards,
Niklas Söderlund
