Hi Russell,
> From: Russell King, Sent: Wednesday, October 19, 2022 8:59 PM
>
> On Wed, Oct 19, 2022 at 12:48:39PM +0200, Marek Behún wrote:
> > On Wed, 19 Oct 2022 17:50:51 +0900
> > Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> >
> > > Add support for selecting host speed mode. For now, only support
> > > 1000M bps.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > > ---
> > > drivers/net/phy/marvell10g.c | 23 +++++++++++++++++++++++
> > > 1 file changed, 23 insertions(+)
> > >
> > > diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
> > > index 383a9c9f36e5..daf3242c6078 100644
> > > --- a/drivers/net/phy/marvell10g.c
> > > +++ b/drivers/net/phy/marvell10g.c
> > > @@ -101,6 +101,10 @@ enum {
> > > MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
> > > MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
> > >
> > > + MV_MOD_CONF = 0xf000,
> > > + MV_MOD_CONF_SPEED_MASK = 0x00c0,
> > > + MV_MOD_CONF_SPEED_1000 = BIT(7),
> > > +
> >
> > Where did you get these values from? My documentation says:
> > Mode Configuration
> > Device 31, Register 0xF000
> > Bits
> > 7:6 Reserved R/W 0x3 This must always be 11.
>
> The closest is from the 88x3310 documentation that indicates these are
> the default speed, which are used when the media side is down. There
> is a specific sequence to update these.
>
> However, as we seem to be talking about the 2110 here, that should be
> reflected in these definitions.
Yes, this is about 2110. So, I'll find other way for my environment somehow.
> Finally, using BIT() for definitions of a field which can be one of
> four possible values is not acceptable. BIT() is for single bits
> not for a multi-bit field which can take any possible value but just
> the value we're representing there just happens to have a single bit
> set.
I understood it. Thanks!
Best regards,
Yoshihiro Shimoda
> --
> RMK's Patch system:
