Hi all,
Currently, the R-Car S4-8 DTS describes a single Cortex-A55 CPU core
only. This patch series completes the description of the Cortex-A55
lusters by describing L3 caches, CPU cores 1-7, CPU map, PSCI for CPU bring up,
CPUIdle, and CPU core clocks.
This has been tested on the Spider development board, where now all 8
Cortex-A55 CPU cores are available after boot. All but the first CPU
core can be controlled from sysfs (/sys/*/*/cpu/cpu[0-7]/online).
CPU core performance follows the CPU core clocks, when changing the
frequency of the latter.
I plan to queue this in renesas-devel for v5.20.
Thanks for your comments!
Geert Uytterhoeven (3):
arm64: dts: renesas: r8a779f0: Add L3 cache controller
arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
arm64: dts: renesas: r8a779f0: Add CPU core clocks
Tho Vu (1):
arm64: dts: renesas: r8a779f0: Add CPUIdle support
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 175 +++++++++++++++++++++-
1 file changed, 170 insertions(+), 5 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
