[PATCH 1/4] arm64: dts: renesas: r8a779f0: Add L3 cache controller

[Geert Uytterhoeven <geert+renesas@xxxxxxxxx>]

Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index ad8c77edb12699d5..41aa23e557179af8 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -23,6 +23,14 @@ a55_0: cpu@0 {
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
+			next-level-cache = <&L3_CA55_0>;
+		};
+
+		L3_CA55_0: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779F0_PD_A2E0D0>;
+			cache-unified;
+			cache-level = <3>;
 		};
 	};
 
-- 
2.25.1