On Wed, May 18, 2022 at 8:32 PM Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote:
> On 18 May 2022 19:25 Ralph Siemsen wrote:
> > There are two UART clock groups, each having a mux to select its
> > upstream clock source. The register/bit definitions for accessing these
> > two muxes appear to have been reversed since introduction. Correct them
> > so as to match the hardware manual.
> >
> > Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
> >
> > Signed-off-by: Ralph Siemsen <ralph.siemsen@xxxxxxxxxx>
> > ---
> > v2 changes:
> > - reverse the comments as well
>
> Reviewed-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
Thanks, will queue in renesas-clk-for-v5.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
