Hi Ralph,
Thanks for your patch!
On 18 May 2022 19:25 Ralph Siemsen wrote:
> There are two UART clock groups, each having a mux to select its
> upstream clock source. The register/bit definitions for accessing these
> two muxes appear to have been reversed since introduction. Correct them
> so as to match the hardware manual.
>
> Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
>
> Signed-off-by: Ralph Siemsen <ralph.siemsen@xxxxxxxxxx>
> ---
> v2 changes:
> - reverse the comments as well
>
> drivers/clk/renesas/r9a06g032-clocks.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
> b/drivers/clk/renesas/r9a06g032-clocks.c
> index c99942f0e4d4..abc0891fd96d 100644
> --- a/drivers/clk/renesas/r9a06g032-clocks.c
> +++ b/drivers/clk/renesas/r9a06g032-clocks.c
> @@ -286,8 +286,8 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
> .name = "uart_group_012",
> .type = K_BITSEL,
> .source = 1 + R9A06G032_DIV_UART,
> - /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
> - .dual.sel = ((0xec / 4) << 5) | 24,
> + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
> + .dual.sel = ((0x34 / 4) << 5) | 30,
> .dual.group = 0,
> },
> {
> @@ -295,8 +295,8 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
> .name = "uart_group_34567",
> .type = K_BITSEL,
> .source = 1 + R9A06G032_DIV_P2_PG,
> - /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
> - .dual.sel = ((0x34 / 4) << 5) | 30,
> + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
> + .dual.sel = ((0xec / 4) << 5) | 24,
> .dual.group = 1,
> },
> D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3,
> 0x1b4, 0x1b5),
> --
> 2.25.1
Reviewed-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
Thanks
Phil
