Hi Linus, Thank you for the review. On Fri, May 13, 2022 at 9:47 PM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: > > On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > > Supported GPIO IRQs by the chip is not always equal to the number of GPIO > > pins. For example on Renesas RZ/G2L SoC where it has GPIO0-122 pins but at > > a give point a maximum of only 32 GPIO pins can be used as IRQ lines in > > the IRQC domain. > > > > This patch adds ngirq member to struct gpio_irq_chip and passes this as a > > size to irq_domain_create_hierarchy()/irq_domain_create_simple() if it is > > being set in the driver otherwise fallbacks to using ngpio. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > As Geert says, I think you can just use .valid_mask for this, > what do you say? > I don't think Geert is suggesting that. The .valid_mask option is one time setting but what I need is something dynamic i.e. out of 392 GPIO pins any 32 can be used as an interrupt pin. Also with this patch we also save on memory [0]. [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/kernel/irq/irqdomain.c?h=next-20220518#n153 Cheers, Prabhakar
