On Sat, May 14, 2022 at 4:14 AM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote: > > On Mon, May 9, 2022 at 7:10 AM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > > Supported GPIO IRQs by the chip is not always equal to the number of GPIO > > pins. For example on Renesas RZ/G2L SoC where it has GPIO0-122 pins but at > > a give point a maximum of only 32 GPIO pins can be used as IRQ lines in > > the IRQC domain. > > > > This patch adds ngirq member to struct gpio_irq_chip and passes this as a > > size to irq_domain_create_hierarchy()/irq_domain_create_simple() if it is > > being set in the driver otherwise fallbacks to using ngpio. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > As mentioned in some other patch, try to use .valid_mask for this instead. I have not been Cc'ed, but briefly reading I agree with Linus. -- With Best Regards, Andy Shevchenko
