Hi Biju,
On Wed, May 4, 2022 at 8:44 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> After adding reset support to vsp, it needs a delay of 32 microseconds
> after reset operation, otherwise system hangs(due to register read/write).
> This patch fixes the system hang issue by adding delay after deassert
> operation.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> After adding reset/deassert support for vsp based on [1],
> RZ/G1N board hangs. On debugging it found that it needs a delay
> of 35 microseconds after deasserint reset. Wthout delay if
> there is any register read/write will lead to hang.
>
> This 35 microseconds value is picked from the reset().
The 35 µs comes from the Hardware User's Manual: there should be
at least 1 RCLK cycle _in between_ asserting and deasserting reset.
The manual doesn't say anything about delays _after_ deasserting reset.
Could it be that the VSP1 driver is actually deasserting reset
too early?
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -637,6 +637,7 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
> dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
>
> writel(bitmask, priv->base + priv->reset_regs[reg]);
> +
Unrelated change.
> return 0;
> }
>
> @@ -651,6 +652,10 @@ static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
> dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
>
> writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
> +
> + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
> + udelay(35);
> +
> return 0;
> }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
