After adding reset support to vsp, it needs a delay of 32 microseconds after reset operation, otherwise system hangs(due to register read/write). This patch fixes the system hang issue by adding delay after deassert operation. Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> --- Hi All, After adding reset/deassert support for vsp based on [1], RZ/G1N board hangs. On debugging it found that it needs a delay of 35 microseconds after deasserint reset. Wthout delay if there is any register read/write will lead to hang. This 35 microseconds value is picked from the reset(). [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220428065333.3108-3-biju.das.jz@xxxxxxxxxxxxxx/ --- drivers/clk/renesas/renesas-cpg-mssr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 5d2c3edbaa14..025a75a3484c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -637,6 +637,7 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); writel(bitmask, priv->base + priv->reset_regs[reg]); + return 0; } @@ -651,6 +652,10 @@ static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); writel(bitmask, priv->base + priv->reset_clear_regs[reg]); + + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + return 0; } -- 2.25.1
