Re: [PATCH 2/3] arm64: dts: renesas: rzg2l-smarc-som: Enable eMMC on SMARC platform

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Hi Biju,

On Fri, Oct 8, 2021 at 2:43 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > Subject: Re: [PATCH 2/3] arm64: dts: renesas: rzg2l-smarc-som: Enable eMMC
> > on SMARC platform
> > On Thu, Oct 7, 2021 at 5:55 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > wrote:
> > > RZ/G2L SoM has both 64Gb eMMC and micro SD connected to SDHI0.
> > >
> > > Both these interfaces are mutually exclusive and the SD0 device
> > > selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2]
> > > switch position.
> > >
> > > This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch
> > > setting logic for device selection between eMMC and microSD slot
> > > connected to SDHI0.
> > >
> > > Set SW1[2] to position 2/OFF for selecting eMMC Set SW1[2] to position
> > > 3/ON for selecting micro SD
> > >
> > > This patch enables eMMC on RZ/G2L SMARC platform by default.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> >
> > > +       vccq_sdhi0: regulator-vccq-sdhi0 {
> > > +               compatible = "regulator-gpio";
> > > +
> > > +               regulator-name = "SDHI0 VccQ";
> > > +               regulator-min-microvolt = <1800000>;
> > > +               regulator-max-microvolt = <3300000>;
> > > +               states = <3300000 1 1800000 0>;
> > > +               regulator-boot-on;
> > > +               gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
> >
> > Is this correct?
> > According to the schematics, the GPIO should be high to select 3.3V.
>
> Yes, But it is "AND" Operation between SD0_DEV_SEL and GPIO_SD0_PWR_SEL.
>
> For eMMC, SD0_PWR_SEL will be always 1.8V
>
> For Micro SD, SD0_PWR_SEL will be 3.3V when GPIO_SD0_PWR_SEL is high
>           SD0_PWR_SEL will be 1.8V when GPIO_SD0_PWR_SEL is low.

Doesn't the first state in states = <3300000 1 1800000 0> correspond
to GPIO_SD0_PWR_SEL being low?

Oh no, the second cell is the GPIO state...
Why is it common to order these in reverse order? :-(

Sorry, you're right. Please ignore my comment, also for the next patch.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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