Hi Rob,
> -----Original Message-----
> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document
> RZ/G2L phy bindings
>
> On Wed, Jun 30, 2021 at 11:29:36AM +0200, Geert Uytterhoeven wrote:
> > Hi Biju,
> >
> > Thanks for your patch!
> >
> > On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > > Document USB phy bindings for RZ/G2L SoC.
> > >
> > > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes.
> > > Apart from this it uses a different OTG-BC interrupt bit for device
> recognition.
> >
> > Nothing about resets? But see below...
> >
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > > v2->v3
> > > * Created a new compatible for RZ/G2L as per Geert's suggestion.
> > > * Added resets required properties for RZ/G2L SoC.
> > > ---
> > > .../bindings/phy/renesas,usb2-phy.yaml | 18
> ++++++++++++++++++
> > > 1 file changed, 18 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > index d5dc5a3cdceb..a7e585ff28dc 100644
> > > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > @@ -30,6 +30,9 @@ properties:
> > > - renesas,usb2-phy-r8a77995 # R-Car D3
> > > - const: renesas,rcar-gen3-usb2-phy
> > >
> > > + - items:
> > > + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > > +
> > > reg:
> > > maxItems: 1
> > >
> > > @@ -91,6 +94,21 @@ required:
> > > - clocks
> > > - '#phy-cells'
> > >
> > > +allOf:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: renesas,usb2-phy-r9a07g044
> > > + then:
> > > + properties:
> > > + resets:
> > > + items:
> > > + - description: USB phy reset
> > > + - description: reset of USB 2.0 host side
> >
> > Do you need the second reset?
> > Looking at your .dtsi patch, the second reset is shared with
> > ehci/ohci, so perhaps it makes sense to drop it from the phy node?
>
> The existing binding has the host reset (and peripheral, but no phy
> reset). Was that a mistake too? Smells like collecting resources the
> driver happens to want, not what the h/w connections are.
On that SoC's there is no USBPHY control IP to control the reset. But PHY
is part of either host block or peripheral block. On RZ/G2L as well PHY is
part of Host block but we have dedicated IP to control the reset.
Regards,
Biju
