Hi Biju,
Thanks for your patch!
On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
> from this it uses a different OTG-BC interrupt bit for device recognition.
Nothing about resets? But see below...
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2->v3
> * Created a new compatible for RZ/G2L as per Geert's suggestion.
> * Added resets required properties for RZ/G2L SoC.
> ---
> .../bindings/phy/renesas,usb2-phy.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> index d5dc5a3cdceb..a7e585ff28dc 100644
> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> @@ -30,6 +30,9 @@ properties:
> - renesas,usb2-phy-r8a77995 # R-Car D3
> - const: renesas,rcar-gen3-usb2-phy
>
> + - items:
> + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> +
> reg:
> maxItems: 1
>
> @@ -91,6 +94,21 @@ required:
> - clocks
> - '#phy-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,usb2-phy-r9a07g044
> + then:
> + properties:
> + resets:
> + items:
> + - description: USB phy reset
> + - description: reset of USB 2.0 host side
Do you need the second reset?
Looking at your .dtsi patch, the second reset is shared with ehci/ohci,
so perhaps it makes sense to drop it from the phy node?
> + required:
> + - resets
> +
> additionalProperties: false
>
> examples:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
