Hi Laurent, Thanks for the feedback. > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote: > > > -----Original Message----- > > > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings > > > > > > Hi Biju, > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das > > > <biju.das.jz@xxxxxxxxxxxxxx> > > > wrote: > > > > Document RZ/G2L DMAC bindings. > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > > > Reviewed-by: Lad Prabhakar > > > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > > > Thanks for your patch! > > > > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > > > > @@ -0,0 +1,132 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML > > > > +1.2 > > > > +--- > > > > +$id: > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F > > > > +devi > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&data=0 > > > > +4%7C > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da > > > > +0c0% > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7 > > > > +CUnk > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik > > > > +1haW > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDej > > > > +p8wo > > > > +Nrx9iO0ht8%3D&reserved=0 > > > > +$schema: > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F > > > > +devi > > > > +cetree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das. > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571 > > > > +da19 > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWF > > > > +pbGZ > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 > > > > +Mn0% > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw > > > > +%3D& > > > > +amp;reserved=0 > > *sigh* > > > > > + > > > > +title: Renesas RZ/G2L DMA Controller > > > > + > > > > +maintainers: > > > > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > > > + > > > > +allOf: > > > > + - $ref: "dma-controller.yaml#" > > > > + > > > > +properties: > > > > + compatible: > > > > + items: > > > > + - enum: > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC} > > > > > > Please use "renesas,r9a07g044-dmac". > > > > OK. Will change. > > > > > > + - const: renesas,rz-dmac > > > > > > Does this need many changes for RZ/A1H and RZ/A2M? > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't > have the board. > > There is some difference in MID bit size. Other wise both identical. > > > > > > > > + renesas,rz-dmac-slavecfg: > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > > > + description: | > > > > + DMA configuration for a slave channel. Each channel must > > > > + have an > > > array of > > > > + 3 items as below. > > > > + first item in the array is MID+RID > > > > > > Already in dmas. > > > > > > > + second item in the array is slave src or dst address > > > > > > As pointed out by Rob, already known by the slave driver. > > > > > > > + third item in the array is channel configuration value. > > > > > > What exactly is this? > > What would prevent the DMA client from passing the configuration to the > DMA channel through the DMA engine API, just like it passes the slave > source or destination address ? On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx. The only way we can distinguish it is from channel configuration value. Cheers, Biju > > > > Does the R-Car DMAC have this too? If yes, how does its driver handle > it? > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we have > channel configuration value With different set of parameter as mentioned > in Table 16.4. > > > > Please see Page 569, Table 16.4 On-Chip Module requests section. > > > > For eg:- as per Rob's suggestion, I have modelled the driver with the > below entries in ALSA driver for playback/record use case. > > > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>, > > <&dmac 0x256 0x10049c1c > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>; > > dma-names = "tx", "rx"; > > > > Using first parameter, it gets dmac channel. using second and third > > parameter it configures the channel. > > -- > Regards, > > Laurent Pinchart
