On Fri, Jan 08, 2021 at 10:06:51AM +0100, Geert Uytterhoeven wrote:
> Hi Wolfram,
>
> On Tue, Jan 5, 2021 at 1:19 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > On Sun, Dec 27, 2020 at 1:19 PM Wolfram Sang
> > <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> > > Because the datasheet is ambigious, copy over the reset values from the
> > > latest BSP.
> > >
> > > Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
>
> > > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> > > @@ -110,7 +110,7 @@ gpio0: gpio@e6058180 {
> > > interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
> > > clocks = <&cpg CPG_MOD 916>;
> > > power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> > > - resets = <&cpg 916>;
> > > + resets = <&cpg 1331>;
> >
> > I doubt the reset topology differs from the clock topology...
> > Let's hope this will be clarified in a datasheet update soon.
>
> I wrote a small test to check which reset bits reset the GPIO blocks.
> I can confirm the original resets values are correct, and using the bits
> marked PFCx in the Software Reset Registers 12/13/14 do not have any
> impact on the GPIO registers.
>
> So the BSP is wrong, and this patch should be dropped.
Thanks for checking!
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