Ensures RWDT remains alert throughout the boot process if enabled.
This patch applies the change to the following SoCs: r8a774a1,
r8a774b1 and r8a774c0.
Signed-off-by: Ulrich Hecht <uli+renesas@xxxxxxxx>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 5 +++++
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 5 +++++
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 5 +++++
3 files changed, 15 insertions(+)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index e05bfa2..be88403 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -239,6 +239,9 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
static const unsigned int r8a774a1_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
+static const unsigned int r8a774a1_never_disable_mod_clks[] __initconst = {
+ MOD_CLK_ID(402), /* RWDT */
+};
/*
* CPG Clock Data
@@ -324,6 +327,8 @@ const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = {
/* Critical Module Clocks */
.crit_mod_clks = r8a774a1_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks),
+ .never_disable_mod_clks = r8a774a1_never_disable_mod_clks,
+ .num_never_disable_mod_clks = ARRAY_SIZE(r8a774a1_never_disable_mod_clks),
/* Callbacks */
.init = r8a774a1_cpg_mssr_init,
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index c9af7091..230a82e 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -235,6 +235,9 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
+static const unsigned int r8a774b1_never_disable_mod_clks[] __initconst = {
+ MOD_CLK_ID(402), /* RWDT */
+};
/*
* CPG Clock Data
@@ -320,6 +323,8 @@ const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = {
/* Critical Module Clocks */
.crit_mod_clks = r8a774b1_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks),
+ .never_disable_mod_clks = r8a774b1_never_disable_mod_clks,
+ .num_never_disable_mod_clks = ARRAY_SIZE(r8a774b1_never_disable_mod_clks),
/* Callbacks */
.init = r8a774b1_cpg_mssr_init,
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index f91e7a4..6bd74de 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -240,6 +240,9 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
static const unsigned int r8a774c0_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
+static const unsigned int r8a774c0_never_disable_mod_clks[] __initconst = {
+ MOD_CLK_ID(402), /* RWDT */
+};
/*
* CPG Clock Data
@@ -289,6 +292,8 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
/* Critical Module Clocks */
.crit_mod_clks = r8a774c0_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks),
+ .never_disable_mod_clks = r8a774c0_never_disable_mod_clks,
+ .num_never_disable_mod_clks = ARRAY_SIZE(r8a774c0_never_disable_mod_clks),
/* Callbacks */
.init = r8a774c0_cpg_mssr_init,
--
2.7.4
