On 12/17/2019 11:43 PM, Geert Uytterhoeven wrote:
[...]
>>>> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
>>>> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
>>>> clk_register_composite() when registering the RPC[D2] clocks...
>>>>
>>>> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
>>>
>>> Thanks for your patch!
>>>
>>> LGTM, so
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>>
>> Thanks. :-)
>>
>>> Now, before I apply this: does this make RPC-IF work?
>>
>> Unfortunately, no. :-/
>
> As per private communication, I understand the problem is elsewhere,
> and this patch itself is working fine, and thus safe to apply?
Yes, I was able to lower the RPC[D2] frequencies but that didn't
really help...
I should mention that CLK_SET_RATE_PARENT logic seemed a bit backward
to me, i.e. how the given clock know the properties of its parent clock...
> Thanks for confirming!
>
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
