On Thu, Aug 10, 2017 at 09:58:50AM +0200, Simon Horman wrote: > On Wed, Aug 09, 2017 at 09:00:41PM +0200, Wolfram Sang wrote: > > There is one SDHI instance on Gen2 which does not have the CBSY bit. > > So, turn CBSY usage into an extra flag and set it accordingly. This has > > the additional advantage that we can also set it for other incarnations > > later. > > What is the run-time effect, if any, of this change? The run-time effect is that a few cycles are saved because CBSY signals ready a bit earlier than SCLKDIVEN. Though, the more important aspect is that docs explicitly say to wait for CBSY. That's why this change was requested although I don't think it will matter much in practice. > > Chris: according to the specs I have, we can enable it for RZ as well. I'll > > send a patch for that in a minute. If you could test this on top of this one, > > that would be much appreciated! Thanks. > > I take it from the above you did a pass of the available documentation to > see which SoCs support this feature. If so, thanks! I don't have docs for R-Car Gen1 SDHI. But given that even Gen2 has one SDHI instance without CBSY and Gen1 is older, my educated guess is that it does not have CBSY.
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