Hi Geert,
On Mon, Apr 24, 2017 at 10:09:10AM +0200, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Mon, Apr 24, 2017 at 10:03 AM, Peter De Schrijver
> <pdeschrijver@xxxxxxxxxx> wrote:
> >> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> >> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> >>
> >> > +static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
> >> > + unsigned long parent_rate)
> >> > +{
> >> > + struct cpg_z_clk *zclk = to_z_clk(hw);
> >> > + unsigned int mult;
> >> > + unsigned int val;
> >> > + unsigned long rate;
> >> > +
> >> > + val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
> >> > + >> CPG_FRQCRC_ZFC_SHIFT;
> >> > + mult = 32 - val;
> >> > +
> >> > + rate = div_u64((u64)parent_rate * mult + 16, 32);
> >> > + /* Round to closest value at 100MHz unit */
> >> > + rate = 100000000*DIV_ROUND_CLOSEST(rate, 100000000);
> >>
> >> Mike, Stephen: what's your opinion about such rounding tricks?
> >
> > Is this an actual divider or a pulse skipper?
>
> Forgive my ignorance, but what is the difference?
A pulse skipper, as the name says, skips pulses. Eg, if you configure the
skipper to 3/4, it will skip 1 input clock pulse out of 4. The pulse width
will be the same as the parent clock pulse width though. A divider stretches
the clock pulse. So the output of a divider configured to 1/2 will have a
pulse width which is twice as large as the pulse width of the input clock.
Cheers,
Peter.
