Hello.
On 11/7/2016 1:09 PM, Geert Uytterhoeven wrote:
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
<geert+renesas@xxxxxxxxx>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
Changes in version 5:
- describe the Z clock as PLL0/VCO divided by 2.
Why did you do that?
I did it because I removed the divisor-by-2 from PLL0.
--- /dev/null
+++ renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -0,0 +1,270 @@
+ DEF_FIXED("z", R8A7743_CLK_Z, CLK_PLL0, 2, 1),
FTR, previous version had
DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
which made the "z" clock configurable.
I see your point -- I should have included the divisor-by-2 into the
common R-Car gen2 driver code instead...
Gr{oetje,eeting}s,
Geert
MBR, Sergei
