From: Lang Cheng <chenglang@xxxxxxxxxx>
For a field in extended QPC, there are four newly added interfaces:
- hr_reg_set(arr, field) can set all bits to 1,
- hr_reg_clear(arr, field) can clear all bits to 0,
- hr_reg_write(arr, field, val) can write a new value,
- hr_reg_read(arr, field) can read the value.
'arr' is the array name of extended QPC, and 'field' is the global bit
offset of the whole array.
Signed-off-by: Lang Cheng <chenglang@xxxxxxxxxx>
Signed-off-by: Weihang Li <liweihang@xxxxxxxxxx>
---
drivers/infiniband/hw/hns/hns_roce_common.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
index f5669ff..ab2386d 100644
--- a/drivers/infiniband/hw/hns/hns_roce_common.h
+++ b/drivers/infiniband/hw/hns/hns_roce_common.h
@@ -53,6 +53,32 @@
#define roce_set_bit(origin, shift, val) \
roce_set_field((origin), (1ul << (shift)), (shift), (val))
+#define hr_reg_set(arr, field) \
+ ((arr)[(field) / 32] |= \
+ cpu_to_le32((field##_W) + \
+ BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr))))
+
+#define hr_reg_clear(arr, field) \
+ ((arr)[(field) / 32] &= \
+ ~cpu_to_le32((field##_W) + \
+ BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr))))
+
+#define hr_reg_write(arr, field, val) \
+ do { \
+ BUILD_BUG_ON((field) / 32 >= ARRAY_SIZE(arr)); \
+ (arr)[(field) / 32] &= ~cpu_to_le32(field##_W); \
+ (arr)[(field) / 32] |= cpu_to_le32( \
+ ((u32)(val) << ((field) % 32)) & (field##_W)); \
+ } while (0)
+
+#define hr_reg_read(arr, field) \
+ (((le32_to_cpu((arr)[(field) / 32]) & (field##_W)) >> (field) % 32) + \
+ BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr)))
+
+#define V3_GENMASK(h, l) \
+ GENMASK(((h) + BUILD_BUG_ON_ZERO(((h) / 32) != ((l) / 32))) % 32, \
+ ((l) + BUILD_BUG_ON_ZERO((h) < (l))) % 32)
+
#define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3
#define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4
--
2.8.1
